1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory system into which data can be written and from which data can be erased, and more particularly, to a nonvolatile semiconductor memory system for use in an apparatus whose operating voltage ranges broadly, from a low voltage to a high voltage.
2. Description of the Related Art
Nonvolatile semiconductor memories, into which data can be electrically written, and from which data can be erased, are generally known as E.sup.2 PROMs (Electrically Erasable Programmable Read-Only Memories). An E.sup.2 PROM chip contains various components. Among these components are: a memory-cell matrix, a row decoder, a column selector, a column decoder, three level shifters, a sense amplifier, an oscillator, a timer, and a voltage booster. The memory-cell matrix comprises a number of memory cells arranged in rows and columns. The row decoder selects one of the rows of memory cells. The column selector selects one of the columns of memory cells. The column decoder controls the column selector. The first level shifter shifts the level of the output of the row decoder and then supplies the output of the row decoder to the memory-cell matrix. The second level shifter shifts the level of the output of the column decoder and then supplies the output of the column decoder to the column selector. The sense amplifier detects the data read from the memory cell which has been selected by the column selector. The third level shifter shifts the level of input data, and supplies this data to the memory-cell matrix so as to write the data into the memory cell which has been selected by the column selector. The oscillator generates a clock signal. The timer generates various control signals from the clock signal generated by the oscillator. The voltage booster is driven by the clock signal, and boosts a power-supply voltage.
The operating power-supply voltages of most E.sup.2 PROMs commercially available at present are 5 V.+-.10%, 4.5 V to 5.5 V. Hence, these E.sup.2 PROMs can be used in apparatuses for industrial use, without causing any problem. If they are to be incorporated into battery-powered apparatuses for general consumers, such as cameras, car audios, IC cards, however, they should operate over a broad range of operating voltage, from about 1.5 V to about 5.5 V.
It is the memory cells, the level shifters, and the oscillator which limit the operating voltage of the conventional E.sup.2 PROM to 5 V.+-.10%. The other components of the E.sup.2 PROM, i.e., the row decoder, the column selector, column decoder, the sense amplifier, the timer can operate over a relatively broad range of voltages since they are CMOS static circuits. Also, the voltage booster can operated over a broad range of voltages since it is a combination circuit comprising diode-connected transistors and coupling capacitors.
FIG. 1 is a sectional view illustrating one of the memory cells incorporated in the conventional E.sup.2 PROM. As is shown in this figure, N-type diffusion layers 101, 102, and 103 are formed in the surface of a P-type semiconductor substrate 100. A channel region 104 is formed in the surface of the substrate 100, located between the diffusion layers 101 and 102. A relatively thick insulating film 105 is formed on the substrate 100. The film 105 has a thin portion 107 located on the diffusion layer 102. An electrode 106, made of polycrystalline silicon, is formed on the insulating film 105 and located above the channel region 104 and the diffusion layer 102. A relatively thick insulating film 108 is formed on the electrode 106, an electrode 109 made of polycrystalline silicon is formed on this insulating film 108. Therefore, the electrode 109 overlaps the electrode 106.
Another channel region 110 is formed in the surface of the substrate 100, located between the diffusion layers 102 and 103. A comparatively thick insulating film 111 is formed on the channel region 110. An electrode 112 made of polycrystalline silicon is formed on this insulating film 111.
The diffusion layer 101 is connected to a source line S, and the diffusion layer 103 is connected to a bit line BL. The electrodes 106, 109, and 112 are the floating-gate electrode, control-gate electrode, and gate electrode of the memory cell, respectively. The control-gate electrode 109 is connected to a control-gate line CG, the gate electrode 112 is connected to a selection-gate line SG.
FIG. 2 is an equivalent circuit diagram showing the memory cell illustrated in FIG. 1. As is understood from FIG. 2, the memory cell comprises two transistors 131 and 132. The transistor 131 has a floating-gate and is designed to store data. Its source and drain are the diffusion layers 101 and 102 (FIG. 1), respectively. The transistor 132 is an ordinary MOS and used to select the data-storage transistor 131. Its source and drain are the diffusion layers 102 and 103 (FIG. 1), respectively.
The memory cell has three operation modes, i.e., data-erasing mode, data-writing mode, and data-reading mode. FIG. 3 shows the voltages applied to the source line S, the bit line BL, the control-gate line CG, and the selection-gate line SG when the memory cell is set to the data-erasing mode, and also the voltages applied to these lines when the memory cell is set to the data-writing mode. Three power-supply voltages are used in the conventional E.sup.2 PROM chip. They are: V.sub.SS, V.sub.CC, and V.sub.PP. In most cases, V.sub.SS =0 V , V.sub.CC =5 V, and V.sub.PP =20 V. The high voltage V.sub.PP (20 V) is obtained by multiplying the external power-supply voltage by means of the voltage-multiplying circuit incorporated in the E.sup.2 PROM chip.
It will be explained how the memory cell operates when set to the data-erasing mode. In the data-erasing mode, also known as "electron injection mode," electrons are injected into the floating-gate electrode 106, thereby to increase the threshold voltage of the data-storage transistor 131. The voltage applied in this mode to the lines BL, SG, CG, and S are 0 V, 20 V, 20 V, and 0 V, respectively. When the selection-gate line SG is set at 20 V, the selection transistor 132 is turned on, whereby 0 V is applied from the bit line BL to the N-type diffusion layer 102, and 20 V is applied to the floating-gate electrode 106 from the control-gate line CG. Hence, an intense electric field is applied to the thin insulating film 107 interposed between the electrode 106 and the N-type diffusion layer 102. A tunnel current therefore flows from the N-type diffusion layer 102 to the floating-gate electrode 106, and electrons are injected into the floating-gate electrode 106. As a result of this, the threshold voltage of the data-storage transistor 131 increases to, for example, about +8 V.
It will be explained how the memory cell operates when set to the data-writing mode. In the data-writing mode, also known as "electron emission mode," electrons are emitted from the electrode 106, thereby to lower the threshold voltage of the data-storage transistor 131. The voltage applied in the data-writing mode to the lines BL, SG, CG, and S are 20 V, 20 V, 0 V, and 5 V, respectively, thereby setting the transistor 131 in a floating condition. When the selection-gate line SG is set at 20 V, the selection transistor 132 is turned on, whereby 20 V is applied from the bit line BL to the N-type diffusion layer 102. Hence, an intense electric field is applied to the thin insulating film 107 in the direction opposite to that direction in which the electric field is applied in the data-erasing mode. A tunnel current therefore flows from the floating-gate electrode 106 to the N-type diffusion layer 102, and electrons are emitted from the floating-gate electrode 106. As a result, the threshold voltage of the data-storage transistor 131 decreases to, for example, about -5 V.
When the memory cell is set to the data-reading mode, 1 V, 5 V, 0 V, and 0 V are applied to the lines BL, SG, CG, and S, respectively. When 5 V is applied to the selection-gate line SG, the selection transistor 132 is turned on, whereby 1 V is applied to the N-type diffusion layer 102. If electrons are being injected into the floating-gate electrode 106 at this time, the threshold voltage of the memory cell is increasing. Hence, the data-storage transistor 131 is not turned on. No current therefore flows between the bit line BL and the source line S, and the bit line BL remains at 1 V. On the other hand, if electrons are being emitted from the floating-gate electrode 106, the threshold voltage of the memory cell is decreasing. Hence, the data-storage transistor 131 is turned on, and a current flows between the bit line BL and the source line S. As a result, the bit line BL is set at 0 V, i.e., the voltage applied to the source electrode S. That is, while the memory cell is set in the data-reading mode, the difference between the two potentials (i.e., 1 V and 0 V) at which the bit line BL can be set is amplified by the sense amplifier, thereby to determine whether "1" or "0" is being read out of the memory cell.
A problem with the memory cell is that the sense amplifier must detects a small potential difference of only 1 V in order to determine whether "1" or "0" is being read out of the memory cell. Here arises the questions of why the potential of the bit line BL should be maintained at 1 V, not being increased to 5 V. It will be explained why. While the memory cell is set to the data-reading mode, the bit line BL is set at 5 V. In this case, the N-type diffusion layer 102 remains at about 5 V, and the electric field generated by the difference of the potential (0 V) of the control gate CG and that (5 V) of the N-type diffusion layer 102 is applied to the thin insulating film 107 through the floating-gate electrode 106.
The manner and direction in which the electric field is applied in the data-reading mode are the same as those in the data-writing mode (i.e., electron emission mode), but the electric field is less intense than in the data-writing mode. If any memory cell into which electrons have been injected is set in the data-reading mode for a long time, the electrons are gradually emitted from the cell due to tunnel effect, inevitably reducing the threshold voltage of the cell. Upon lapse of a certain period of time, the data stored in the memory cell can no longer be read out correctly. This undesirable phenomenon is called "soft writing," and said period of time is called "read retention characteristic."
In order to improve the read retention characteristic, it necessary to lower the voltage on the bit line BL in the data-reading mode. When this voltage is reduced, however, the difference between the voltage applied to the bit line BL while electrons are being injected into the cell and the voltage applied to the bit line BL while electrons are being emitted from the cell decreases, thus reducing the logic margin of the memory cell. Therefore, in the conventional E.sup.2 PROM, the bit-line voltage is set at about 1 V to impart a sufficient read retention characteristic to each memory cell, and a high-efficiency sense amplifier is used to give a sufficient logic margin to each memory cell. Since the sense amplifier has a high efficiency, the margin of its operating voltage is too small for the reading of data from each memory cell shown in FIG. 1. In other words, the data can hardly be read from the cell when the sense amplifier is driven by a relatively low voltage.
FIG. 4 is a circuit diagram illustrating one of the level shifters incorporated in the conventional E.sup.2 PROM. As is shown in this figure, the level shifter comprises a capacitor 144 and two N-channel MOS transistors 142 and 145. The gate of the transistor 142 is connected to an input terminal 141, and the drain of this transistor is connected to a terminal 143 to which a high voltage V.sub.PP or an ordinary power-supply voltage V.sub.CC is applied. A clock signal is supplied to the source of the transistor 142 through the capacitor 144. The source-drain path of the transistor 145 is connected between the source and drain of the transistor 142. The gate of the transistor 145 is coupled to the source of the transistor 152.
When the clock signal is supplied to one end of the capacitor 144, the source voltage of the transistor 142 increases. The high source voltage of the transistor 142 is applied to the gate of the transistor 142 via the transistor 145, thereby gradually decreasing the conduction resistance of the transistor 142. As a result of this, the high voltage VPP is applied to the input terminal 141 through the transistors 142 and 145, to shift the level of the input data, that of the output of the row decoder, or that of the level of the column decoder.
When the power-supply voltage of the level shifter is low, the amplitude of the clock signal become proportionally small. Thus, the capacitor 144 can no longer increases the source voltage of the transistor 142 to an adequate degree. Consequently, the high voltage V.sub.PP cannot be completely applied to the input terminal 141 through the transistor 142 or 145. Hence, the level shifter cannot achieve a complete level shifting. In view of this, the level shifter shown in FIG. 4 cannot perform its function well when driven by a relatively low voltage, just like the memory cell shown in FIGS. 1 and 2.
The oscillator for generating the clock signal comprises a ring oscillator in most cases. The oscillation frequency of the ring oscillator directly depend upon the power-supply voltage. When the power-supply voltage is 5.+-.10%, the oscillator may have an optimal oscillation frequency. However, the oscillation frequency falls very much when the power-supply voltage is as low as 1.5 V. Inevitably, the voltage generated by the voltage-multiplying circuit cannot be high enough to write data into, or erase data from, any memory cell of the conventional E.sup.2 PROM.
Since the operating voltage of the conventional E.sup.2 PROM falls within an extremely narrow range, the E.sup.2 PROM cannot be driven by means of batteries.